diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-01-03 00:49:45 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-22 20:23:17 +0100 |
| commit | eee4f6b224b897184327539fcbeb23f9b26f02d9 (patch) | |
| tree | 4b16cd646deb66fdcfdde8954798b1698666e155 /src/northbridge/intel/x4x/raminit.c | |
| parent | acbb70b810c6eb17e403c37fa2888b479e5b23a9 (diff) | |
nb/x4x/raminit: Fix programming dram timings
The results were obtained by comparing the MCHBAR registers of vendor bios
with coreboot at the same dram timings.
This fixes 2 issues:
* 1333MHz fsb CPUs were limited to 667MHz ddr2 speeds, because with
800MHz raminit failed;
* 1067MHz fsb CPUs did not boot when second dimm slot was populated.
TESTED on ga-g41m-es2l on 800, 1067 and 1333MHz CPUs with
DDR2 667 and 800MHz dimms.
Change-Id: I70f554f97b44947c2c78713b4d73a47c06d7ba60
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18022
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/x4x/raminit.c')
| -rw-r--r-- | src/northbridge/intel/x4x/raminit.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 122cab50ea..86f63f1bef 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -228,9 +228,7 @@ static void sdram_detect_ram_speed(struct sysinfo *s) // Max RAM speed if (s->spd_type == DDR2) { - // FIXME: Limit memory speed to 667MHz if FSB is 1333MHz - maxfreq = (s->max_fsb == FSB_CLOCK_1333MHz) - ? MEM_CLOCK_667MHz : MEM_CLOCK_800MHz; + maxfreq = MEM_CLOCK_800MHz; // Choose common CAS latency from {6,5}, 4 does not work commoncas = 0x60; |