From eee4f6b224b897184327539fcbeb23f9b26f02d9 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 3 Jan 2017 00:49:45 +0100 Subject: nb/x4x/raminit: Fix programming dram timings The results were obtained by comparing the MCHBAR registers of vendor bios with coreboot at the same dram timings. This fixes 2 issues: * 1333MHz fsb CPUs were limited to 667MHz ddr2 speeds, because with 800MHz raminit failed; * 1067MHz fsb CPUs did not boot when second dimm slot was populated. TESTED on ga-g41m-es2l on 800, 1067 and 1333MHz CPUs with DDR2 667 and 800MHz dimms. Change-Id: I70f554f97b44947c2c78713b4d73a47c06d7ba60 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/18022 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/x4x/raminit.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/northbridge/intel/x4x/raminit.c') diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 122cab50ea..86f63f1bef 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -228,9 +228,7 @@ static void sdram_detect_ram_speed(struct sysinfo *s) // Max RAM speed if (s->spd_type == DDR2) { - // FIXME: Limit memory speed to 667MHz if FSB is 1333MHz - maxfreq = (s->max_fsb == FSB_CLOCK_1333MHz) - ? MEM_CLOCK_667MHz : MEM_CLOCK_800MHz; + maxfreq = MEM_CLOCK_800MHz; // Choose common CAS latency from {6,5}, 4 does not work commoncas = 0x60; -- cgit v1.2.3