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authorAngel Pons <th3fanbus@gmail.com>2020-11-02 22:21:54 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-04-21 09:01:28 +0000
commitf9c939029bf0c07bab7ce623b99d8abcc69f8362 (patch)
tree0d4e2c812867a8e0dd96175bb8fc0c5a0c4db4dd /src/northbridge/intel/x4x/early_init.c
parent9dc1c51db47f43190c9396e9dd77f051530265a4 (diff)
nb/intel: Use get_int_option()
Change-Id: I8896531d6df729709456bc6e79e02136d9ea7b3b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge/intel/x4x/early_init.c')
-rw-r--r--src/northbridge/intel/x4x/early_init.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index de261bda7d..1de9e2868b 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -38,9 +38,8 @@ void x4x_early_init(void)
/* Enable internal GFX */
pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, BOARD_DEVEN);
- /* Set preallocated IGD size from CMOS */
- u8 gfxsize = 6; /* 6 for 64MiB, default if not set in CMOS */
- get_option(&gfxsize, "gfx_uma_size");
+ /* Set preallocated IGD size from CMOS, or default to 64 MiB */
+ u8 gfxsize = get_int_option("gfx_uma_size", 6);
if (gfxsize > 12)
gfxsize = 6;
/* Need at least 4M for cbmem_top alignment */