nb/intel/x4x: Reflow long lines

Try to unbreak long lines and user-visible strings.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I1bbf08cf665157840380517302ca581718e3cbe4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51874
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 25 insertions, 47 deletions

diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c
index eab5365341..afb77424af 100644
--- a/src/northbridge/intel/x4x/dq_dqs.c
+++ b/src/northbridge/intel/x4x/dq_dqs.c
@@ -8,8 +8,7 @@
 #include "raminit.h"
 #include "x4x.h"
 
-static void print_dll_setting(const struct dll_setting *dll_setting,
-			u8 default_verbose)
+static void print_dll_setting(const struct dll_setting *dll_setting, u8 default_verbose)
 {
 	u8 debug_level = default_verbose ? BIOS_DEBUG : RAM_DEBUG;
 
@@ -75,11 +74,9 @@ static void set_db(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
 
 static const u8 max_tap[3] = {12, 10, 13};
 
-static int increment_dq_dqs(const struct sysinfo *s,
-			struct dll_setting *dq_dqs_setting)
+static int increment_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
 {
-	u8 max_tap_val = max_tap[s->selected_timings.mem_clk
-				- MEM_CLOCK_800MHz];
+	u8 max_tap_val = max_tap[s->selected_timings.mem_clk - MEM_CLOCK_800MHz];
 
 	if (dq_dqs_setting->pi < 6) {
 		dq_dqs_setting->pi += 1;
@@ -102,11 +99,9 @@ static int increment_dq_dqs(const struct sysinfo *s,
 	return CB_SUCCESS;
 }
 
-static int decrement_dq_dqs(const struct sysinfo *s,
-			struct dll_setting *dq_dqs_setting)
+static int decrement_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
 {
-	u8 max_tap_val = max_tap[s->selected_timings.mem_clk
-				- MEM_CLOCK_800MHz];
+	u8 max_tap_val = max_tap[s->selected_timings.mem_clk - MEM_CLOCK_800MHz];
 
 	if (dq_dqs_setting->pi > 0) {
 		dq_dqs_setting->pi -= 1;
@@ -159,8 +154,7 @@ enum training_modes {
 	FAILING = 1
 };
 
-static u8 test_dq_aligned(const struct sysinfo *s,
-					const u8 channel)
+static u8 test_dq_aligned(const struct sysinfo *s, const u8 channel)
 {
 	u32 address;
 	int rank, lane;
@@ -174,17 +168,14 @@ static u8 test_dq_aligned(const struct sysinfo *s,
 			for (count1 = 0; count1 < WT_PATTERN_SIZE; count1++) {
 				if ((count1 % 16) == 0)
 					MCHBAR32(0xf90) = 1;
-				const u32 pattern =
-					write_training_schedule[count1];
+				const u32 pattern = write_training_schedule[count1];
 				write32((u32 *)address + 8 * count1, pattern);
-				write32((u32 *)address + 8 * count1 + 4,
-					pattern);
+				write32((u32 *)address + 8 * count1 + 4, pattern);
 			}
 
 			const u32 good = write_training_schedule[count];
 			write32(&data[0], read32((u32 *)address + 8 * count));
-			write32(&data[4],
-				read32((u32 *)address + 8 * count + 4));
+			write32(&data[4], read32((u32 *)address + 8 * count + 4));
 			FOR_EACH_BYTELANE(lane) {
 				u8 expected = (good >> ((lane % 4) * 8)) & 0xff;
 				if (data[lane] != expected)
@@ -235,8 +226,8 @@ static int find_dq_limit(const struct sysinfo *s, const u8 channel,
 				success_mask &= ~(1 << lane);
 			}
 			if (status == CB_ERR) {
-				printk(BIOS_CRIT, "Could not find a case of %s "
-					"writes on CH%d, lane %d\n",
+				printk(BIOS_CRIT,
+					"Could not find a case of %s writes on CH%d, lane %d\n",
 					expected_result == FAILING ? "failing"
 					: "succeeding", channel, lane);
 				return CB_ERR;
@@ -281,19 +272,15 @@ int do_write_training(struct sysinfo *s)
 		/* Start from DQS settings */
 		memcpy(dq_setting, s->dqs_settings[channel], sizeof(dq_setting));
 
-		if (find_dq_limit(s, channel, dq_setting, dq_lower,
-					SUCCEEDING)) {
-			printk(BIOS_CRIT,
-				"Could not find working lower limit DQ setting\n");
+		if (find_dq_limit(s, channel, dq_setting, dq_lower, SUCCEEDING)) {
+			printk(BIOS_CRIT, "Could not find working lower limit DQ setting\n");
 			return CB_ERR;
 		}
 
 		memcpy(dq_upper, dq_lower, sizeof(dq_lower));
 
-		if (find_dq_limit(s, channel, dq_setting, dq_upper,
-					FAILING)) {
-			printk(BIOS_WARNING,
-				"Could not find failing upper limit DQ setting\n");
+		if (find_dq_limit(s, channel, dq_setting, dq_upper, FAILING)) {
+			printk(BIOS_WARNING, "Could not find failing upper limit DQ setting\n");
 			return CB_ERR;
 		}
 
@@ -302,8 +289,8 @@ int do_write_training(struct sysinfo *s)
 			dq_upper[lane] -= CONSISTENCY - 1;
 			u8 dq_center = (dq_upper[lane] + dq_lower[lane]) / 2;
 
-			printk(RAM_DEBUG, "Centered value for DQ DLL:"
-				" ch%d, lane %d, #steps = %d\n",
+			printk(RAM_DEBUG,
+				"Centered value for DQ DLL: ch%d, lane %d, #steps = %d\n",
 				channel, lane, dq_center);
 			for (i = 0; i < dq_center; i++) {
 				/* Should never happen */
@@ -403,13 +390,10 @@ static int rt_find_dqs_limit(struct sysinfo *s, u8 channel,
 	}
 
 	if (expected_result == SUCCEEDING) {
-		printk(BIOS_CRIT,
-			"Could not find RT DQS setting\n");
+		printk(BIOS_CRIT, "Could not find RT DQS setting\n");
 		return CB_ERR;
 	} else {
-		printk(RAM_DEBUG,
-			"Read succeeded over all DQS"
-			" settings, continuing\n");
+		printk(RAM_DEBUG, "Read succeeded over all DQS settings, continuing\n");
 		return CB_SUCCESS;
 	}
 }
@@ -664,8 +648,7 @@ static enum cb_err increment_to_dqs_edge(struct sysinfo *s, u8 channel, u8 rank)
 			if (bytelane_ok & (1 << lane))
 				continue;
 
-			printk(RAM_SPEW, "%d, %d, %02d, %d,"
-				" lane%d sample: %d\n",
+			printk(RAM_SPEW, "%d, %d, %02d, %d, lane%d sample: %d\n",
 				dqs_setting[lane].coarse,
 				dqs_setting[lane].clk_delay,
 				dqs_setting[lane].tap,
@@ -785,8 +768,7 @@ void search_write_leveling(struct sysinfo *s)
 		printk(BIOS_DEBUG, "\tCH%d\n", ch);
 		config = chanconfig_lut[s->dimm_config[ch]];
 
-		MCHBAR8(0x5d8 + 0x400 * ch) =
-			MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e;
+		MCHBAR8(0x5d8 + 0x400 * ch) = MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e;
 		MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) &
 						~0x3fff) | 0x3fff;
 		MCHBAR8(0x265 + 0x400 * ch) =
@@ -803,12 +785,9 @@ void search_write_leveling(struct sysinfo *s)
 		MCHBAR8(0x298 + 2 + 0x400 * ch) =
 			(MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f)
 			| odt_force[config][rank0];
-		MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch)
-					& ~0x7e) | 0x4e;
-		MCHBAR8(0x5d9 + 0x400 * ch) =
-			(MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04) | 0x04;
-		MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff)
-			| 0x00014000;
+		MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch) & ~0x7e) | 0x4e;
+		MCHBAR8(0x5d9 + 0x400 * ch) = (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04) | 0x04;
+		MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff) | 0x00014000;
 
 		if (increment_to_dqs_edge(s, ch, rank0))
 			die("Write Leveling failed!");
@@ -827,8 +806,7 @@ void search_write_leveling(struct sysinfo *s)
 		set_rank_write_level(s, ch, config, rank0, rank0, 0);
 		send_jedec_cmd(s, rank0, ch, NORMALOP_CMD, 1 << 12);
 
-		MCHBAR8(0x5d8 + 0x400 * ch) = (MCHBAR8(0x5d8 + 0x400 * ch)
-					& ~0x0e) | 0x0e;
+		MCHBAR8(0x5d8 + 0x400 * ch) = (MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e) | 0x0e;
 		MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch)
 						& ~0x3fff) | 0x1807;
 		MCHBAR8(0x265 + 0x400 * ch) = MCHBAR8(0x265 + 0x400 * ch) & ~0x1f;