diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 13:23:18 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-30 23:12:44 +0000 |
| commit | bbc80f4405a1ba12ad444ef900da6a55d63f45b8 (patch) | |
| tree | 85249be08e8da68f9f7d1aaa5d09454f00febb83 /src/northbridge/intel/x4x/acpi.c | |
| parent | 1318ab475ddcae5fdd8f41b66c4d7034c8b3d396 (diff) | |
nb/intel/x4x: Define and use MMCONF_BUS_NUMBER
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Moreover, the ASL reservation for MMCONFIG was only for 64 busses.
Change-Id: I7366a5096aacd92401535be020358447650b4247
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/x4x/acpi.c')
| -rw-r--r-- | src/northbridge/intel/x4x/acpi.c | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index 4088e75dae..8f94b3454b 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <console/console.h> #include <acpi/acpi.h> #include <acpi/acpigen.h> @@ -9,13 +8,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - u32 pciexbar, length; - - if (!decode_pcie_bar(&pciexbar, &length)) - return current; - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, (length >> 20) - 1); + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); return current; } |