From bbc80f4405a1ba12ad444ef900da6a55d63f45b8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 20 Jan 2021 13:23:18 +0100 Subject: nb/intel/x4x: Define and use MMCONF_BUS_NUMBER Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR register. The `length` bitfield was set to 0, so assume 256 busses. Moreover, the ASL reservation for MMCONFIG was only for 64 busses. Change-Id: I7366a5096aacd92401535be020358447650b4247 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/x4x/acpi.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'src/northbridge/intel/x4x/acpi.c') diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index 4088e75dae..8f94b3454b 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -9,13 +8,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - u32 pciexbar, length; - - if (!decode_pcie_bar(&pciexbar, &length)) - return current; - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, (length >> 20) - 1); + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); return current; } -- cgit v1.2.3