nb/intel/x4x: Refactor setting default dll settings

This patch pushes these large default delay tables to a different file
to reduce cluttering up the actual raminit source. While doing so it
also uses more but smaller arrays and also adds the respective default
delays for DDR3 which are not yet used in this patch.

This patch add a function to set the read DQS delays instead of just
programming magic values. (This will prove useful for DQS read
training)

To prepare for adding trainings on the delay values it stores these
default delays in the sysinfo struct to program those. Later when
trainings are implemented those trained values will be used instead of
these safe default values, via using the cached sysinfo in 'mrc'
cache.

TESTED on DG43GT (still works fine)

Change-Id: I0e3676e06586ea84fc0729469946dbc9a8225934
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 1 insertions, 0 deletions

diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc
index 5c64ca7e49..fb9dc1591b 100644
--- a/src/northbridge/intel/x4x/Makefile.inc
+++ b/src/northbridge/intel/x4x/Makefile.inc
@@ -21,6 +21,7 @@ romstage-y += raminit.c
 romstage-y += raminit_ddr2.c
 romstage-y += ram_calc.c
 romstage-y += rcven.c
+romstage-y += raminit_tables.c
 
 ramstage-y += acpi.c
 ramstage-y += ram_calc.c