From 0bf87de667f22399f7a0b110ce29222f3aba5484 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 4 Nov 2017 06:15:05 +0100 Subject: nb/intel/x4x: Refactor setting default dll settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch pushes these large default delay tables to a different file to reduce cluttering up the actual raminit source. While doing so it also uses more but smaller arrays and also adds the respective default delays for DDR3 which are not yet used in this patch. This patch add a function to set the read DQS delays instead of just programming magic values. (This will prove useful for DQS read training) To prepare for adding trainings on the delay values it stores these default delays in the sysinfo struct to program those. Later when trainings are implemented those trained values will be used instead of these safe default values, via using the cached sysinfo in 'mrc' cache. TESTED on DG43GT (still works fine) Change-Id: I0e3676e06586ea84fc0729469946dbc9a8225934 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/22327 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer Reviewed-by: Felix Held --- src/northbridge/intel/x4x/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/northbridge/intel/x4x/Makefile.inc') diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 5c64ca7e49..fb9dc1591b 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -21,6 +21,7 @@ romstage-y += raminit.c romstage-y += raminit_ddr2.c romstage-y += ram_calc.c romstage-y += rcven.c +romstage-y += raminit_tables.c ramstage-y += acpi.c ramstage-y += ram_calc.c -- cgit v1.2.3