diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 13:34:24 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-03 10:18:56 +0000 |
| commit | 4c65bfc3e88fe6f4d6441fb7e51f78ed22dea709 (patch) | |
| tree | 4e2a75d7f1c967e57bf20f7a2854695c69d37cec /src/northbridge/intel/x4x/Kconfig | |
| parent | cf3076eff17dc9c152fca6ec9012e7734ff88b4c (diff) | |
nb/intel/x4x: Use common code for SMM in TSEG
This also caches the TSEG region and therefore increases MTRR usage
a little in some cases.
Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.
Tested on Intel DG41WV, resume from S3 still works fine.
Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25597
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/x4x/Kconfig')
| -rw-r--r-- | src/northbridge/intel/x4x/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 1c65614d9d..117ac03882 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -28,6 +28,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select CACHE_MRC_SETTINGS select POSTCAR_STAGE select POSTCAR_CONSOLE + select SMM_TSEG config CBFS_SIZE hex |