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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-05-03 15:53:33 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-05-17 21:38:17 +0200 |
| commit | 4bab6e79b078c76d0a42883c4b4c9c68615d5a1e (patch) | |
| tree | 2c7dda58587f464fa1baee712c95bb48c924ff76 /src/northbridge/intel/sch/sch.h | |
| parent | 083da160af4a0e3a76506af59477f105d78b9683 (diff) | |
intel/sch: Merge northbridge and southbridge in src/soc
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14599
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sch/sch.h')
| -rw-r--r-- | src/northbridge/intel/sch/sch.h | 50 |
1 files changed, 0 insertions, 50 deletions
diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h deleted file mode 100644 index 5bb65b3a70..0000000000 --- a/src/northbridge/intel/sch/sch.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2009-2010 iWave Systems - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SCH_PULSBO_H__ -#define __SCH_PULSBO_H__ - -int sch_port_access_read(int port, int reg, int bytes); -void sch_port_access_write(int port, int reg, int bytes, long data); -void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data); - -/* Southbridge IO BARs */ -/* TODO Make sure these don't get changed by stage2 */ -#define SCH_ENABLE_BIT (1<<31) -#define DEFAULT_ACPIPBLKBASE 0x510 - -#define DEFAULT_SMBUSBASE 0x540 -#define DEFAULT_GPIOBASE 0x588 -#define DEFAULT_GPE0BASE 0x5C0 -#define DEFAULT_SMMCNTRLBASE 0x3F703F76 - -#define DEFAULT_RCBABASE ((u8 *)0xfed1c000) - -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ - -/* IGD */ -#define GGC 0x52 - -/* Root Complex Register Block */ -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBABASE + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBABASE + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBABASE + x)) - -/* FIXME: should probably be in southbridge, but is setup in romstage, too */ -#define CMC_SHADOW 0x3faf0000 - -#endif /* __SCH_PULSBO_H__ */ |