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authorShuo Liu <shuo.liu@intel.com>2024-06-25 18:50:06 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-06-26 18:07:30 +0000
commitf3aaa0e1539c16a3a26a769110ec1aca458ab410 (patch)
tree30a9a682a32c882eee4252fb44868c1b7a3565a5 /src/northbridge/intel/sandybridge
parent79d7f3a13ed59515bee0d043c3fda79854201858 (diff)
acpi: Rename acpi_create_dmar_drhd
For most of SoCs, DRHD is by default with the size of 4KB. However, larger sizes are allowed as well. Rename acpi_create_dmar_drhd to acpi_create_dmar_drhd_4k to support the default case while a later patch will re-add acpi_create_dmar_drhd with a size parameter. TEST=intel/archercity CRB Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
-rw-r--r--src/northbridge/intel/sandybridge/acpi.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index 8be161ec05..3ffab4d44c 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -34,14 +34,14 @@ static unsigned long acpi_fill_dmar(unsigned long current)
if (igfx && igfx->enabled) {
const unsigned long tmp = current;
- current += acpi_create_dmar_drhd(current, 0, 0, GFXVT_BASE);
+ current += acpi_create_dmar_drhd_4k(current, 0, 0, GFXVT_BASE);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current);
}
{
const unsigned long tmp = current;
- current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE);
+ current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE);
current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR,
PCH_IOAPIC_PCI_BUS,