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authorArthur Heymans <arthur@aheymans.xyz>2018-06-03 12:04:26 +0200
committerArthur Heymans <arthur@aheymans.xyz>2018-06-05 07:49:41 +0000
commitdd4d8951368029634f53e44e1a222417b72036c0 (patch)
tree145e103037040f09438d5e41895ab0c6e51db4fe /src/northbridge/intel/sandybridge
parent3a4edb6ea815fa24f02daeae9b80e6bde0871a9e (diff)
cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support
Prepare a common cache as ram for CPU's featuring a Non eviction mode MSR. Change-Id: I7fa3853498856050855b3b97546f4d31f66d12f7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26789 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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