diff options
| author | Jes Klinke <jbk@google.com> | 2020-07-29 14:22:41 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2020-08-20 19:34:46 +0000 |
| commit | dcae8074bf7f575a267b4253b1242e5cbc9565c7 (patch) | |
| tree | 6f758486bb67233651c0a780698e0b42cfb3dd1b /src/northbridge/intel/sandybridge | |
| parent | f290e6298f215e92598144a404571aaf32581154 (diff) | |
drivers/spi/tpm: Enable long cr50 ready pulses for Tiger Lake systems
For Volteer (and future Tiger Lake boards) we can enable mode S0i3.4
only if we know that the Cr50 is generating 100us interrupt pulses.
We have to do so, because the SoC is not guaranteed to detect pulses
shorter than 100us in S0i3.4 substate.
A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code
running in verstage, which will program a new Cr50 register, provided that
Cr50 firmware is new enough to support the register.
BUG=b:154333137
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Change-Id: If83188fd09fe69c2cda4ce1a8bf5b2efe1ca86da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
0 files changed, 0 insertions, 0 deletions