coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

8 files changed, 13 insertions, 13 deletions

diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
index 73692037c3..dce9f67029 100644
--- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
@@ -35,7 +35,7 @@ Device (PDRC)
 		Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
 		Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
 
-#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
+#if CONFIG(CHROMEOS_RAMOOPS)
 		Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
 					 CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
 #endif
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 44eebf3215..ad579c6fc3 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -59,7 +59,7 @@ static void sandybridge_setup_bars(void)
 	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
 	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
 
-#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
+#if CONFIG(ELOG_BOOT_COUNT)
 	/* Increment Boot Counter for non-S3 resume */
 	if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
 	    ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
@@ -68,7 +68,7 @@ static void sandybridge_setup_bars(void)
 
 	printk(BIOS_DEBUG, " done.\n");
 
-#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
+#if CONFIG(ELOG_BOOT_COUNT)
 	/* Increment Boot Counter except when resuming from S3 */
 	if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
 	    ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)
@@ -159,7 +159,7 @@ static void start_peg_link_training(void)
 	 * As the MRC has its own initialization code skip it. */
 	if (((pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID) &
 			BASE_REV_MASK) != BASE_REV_IVB) ||
-		IS_ENABLED(CONFIG_HAVE_MRC))
+		CONFIG(HAVE_MRC))
 		return;
 
 	deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index ce2abd9d88..00180fe4f0 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -625,7 +625,7 @@ static void gma_func0_init(struct device *dev)
 	/* Init graphics power management */
 	gma_pm_init_pre_vbios(dev);
 
-	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+	if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT))
 		/* PCI Init, will run VBIOS */
 		pci_dev_init(dev);
 
@@ -636,7 +636,7 @@ static void gma_func0_init(struct device *dev)
 
 	/* Running graphics init on S3 breaks Linux drm driver. */
 	if (!acpi_is_wakeup_s3() &&
-	    IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
+	    CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
 		if (vga_disable) {
 			printk(BIOS_INFO,
 			       "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n");
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index ab0554c7df..e58a0ebc3a 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -98,7 +98,7 @@ static void add_fixed_resources(struct device *dev, int index)
 	reserved_ram_resource(dev, index++, 0xc0000 >> 10,
 			(0x100000 - 0xc0000) >> 10);
 
-#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
+#if CONFIG(CHROMEOS_RAMOOPS)
 	reserved_ram_resource(dev, index++,
 			CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
 			CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c
index 53fb4d3530..16bc314b90 100644
--- a/src/northbridge/intel/sandybridge/pcie.c
+++ b/src/northbridge/intel/sandybridge/pcie.c
@@ -28,7 +28,7 @@ static void pcie_disable(struct device *dev)
 	dev->enabled = 0;
 }
 
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 static const char *pcie_acpi_name(const struct device *dev)
 {
 	assert(dev);
@@ -90,7 +90,7 @@ static struct device_operations device_ops = {
 	.disable		= pcie_disable,
 	.init			= pci_dev_init,
 	.ops_pci		= &pci_ops,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 	.acpi_name		= pcie_acpi_name,
 #endif
 };
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index caba76efac..3f62d10a1c 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -210,7 +210,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
 				printram("XMP profile supports %u DIMMs, but %u DIMMs are installed.\n",
 						 dimm->dimm[channel][slot].dimms_per_channel,
 						 dimms_on_channel);
-				if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS))
+				if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS))
 					printk(BIOS_WARNING, "XMP maximum DIMMs will be ignored.\n");
 				else
 					spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]);
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 6bda9ed3dd..fda662f4f6 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -390,7 +390,7 @@ unsigned int get_mem_min_tck(void)
 
 	/* If this is zero, it just means devicetree.cb didn't set it */
 	if (!cfg || cfg->max_mem_clock_mhz == 0) {
-		if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
+		if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
 			return TCK_1333MHZ;
 
 		rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 853fdb83d0..852da7aa26 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -41,7 +41,7 @@
  * MRC scrambler seed offsets should be reserved in
  * mainboard cmos.layout and not covered by checksum.
  */
-#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
+#if CONFIG(USE_OPTION_TABLE)
 #include "option_table.h"
 #define CMOS_OFFSET_MRC_SEED     (CMOS_VSTART_mrc_scrambler_seed >> 3)
 #define CMOS_OFFSET_MRC_SEED_S3  (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3)
@@ -241,7 +241,7 @@ void sdram_initialize(struct pei_data *pei_data)
 	}
 
 	/* mrc.bin reconfigures USB, so reinit it to have debug */
-	if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM))
+	if (CONFIG(USBDEBUG_IN_PRE_RAM))
 		usbdebug_hw_init(true);
 
 	/* For reference print the System Agent version