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authorVladimir Serbinenko <phcoder@gmail.com>2014-08-03 01:59:38 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2014-08-03 13:44:40 +0200
commit5fc04d1fdd2d4c763ba39c3d90e487e9f773b122 (patch)
treedc52c1353822be15d6026799741c8b38ee68ae78 /src/northbridge/intel/sandybridge
parent96639fb7db099dbaad4e70dd5179cd6f2f636b57 (diff)
sandy/ivybridge: Make UMA size configurable.
Change-Id: I9aa3652d1b92cece01d024e19bdc065797896001 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6470 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
-rw-r--r--src/northbridge/intel/sandybridge/early_init.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index d688f5b5a1..d1d35dbab2 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -24,6 +24,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <elog.h>
+#include <pc80/mc146818rtc.h>
#include "sandybridge.h"
static void sandybridge_setup_bars(void)
@@ -83,6 +84,7 @@ static void sandybridge_setup_graphics(void)
u32 reg32;
u16 reg16;
u8 reg8;
+ u8 gfxsize;
reg16 = pci_read_config16(PCI_DEV(0,2,0), PCI_DEVICE_ID);
switch (reg16) {
@@ -103,10 +105,13 @@ static void sandybridge_setup_graphics(void)
printk(BIOS_DEBUG, "Initializing Graphics...\n");
- /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
+ if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
+ /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
+ gfxsize = 0;
+ }
reg16 = pci_read_config16(PCI_DEV(0,0,0), GGC);
reg16 &= ~0x00f8;
- reg16 |= 1 << 3;
+ reg16 |= (gfxsize + 1) << 3;
/* Program GTT memory by setting GGC[9:8] = 2MB */
reg16 &= ~0x0300;
reg16 |= 2 << 8;