diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-05-14 12:55:17 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-15 17:58:59 +0000 |
| commit | 274dabd7a04b18bc2f2378bb9faa7416dfd0ab83 (patch) | |
| tree | a53f87b1200b13ced01afccd389963bb8e7c6d81 /src/northbridge/intel/sandybridge | |
| parent | 45b79be9c06ccc925eeb3c11e821413478b903b5 (diff) | |
src/northbridge: Remove unneeded include <arch/io.h>
Change-Id: I52ace93ae6f802723823955ac349ed54dc064aaa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 1 |
3 files changed, 0 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index e60c37875b..2ebeaf0dca 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -21,7 +21,6 @@ #include <cf9_reset.h> #include <string.h> #include <arch/cpu.h> -#include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <cbmem.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index a35d9d814e..f032b8aefc 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -18,7 +18,6 @@ #include <bootmode.h> #include <cf9_reset.h> #include <string.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <arch/cpu.h> #include <cbmem.h> diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 064d042e56..76b3088388 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <console/console.h> -#include <arch/io.h> #include <cf9_reset.h> #include <device/pci_ops.h> #include <cpu/x86/lapic.h> |