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| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2021-12-01 10:12:28 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-12-02 16:37:32 +0000 |
| commit | 1ce0f3aab72dab7a74277a8eda6e6605edf106e3 (patch) | |
| tree | e5261e00f62419dfaa3a388faec525350606422c /src/northbridge/intel/sandybridge | |
| parent | db925aaf38dfc10de74c80cb1e43a7058fa8811a (diff) | |
mb/google/brya: Fix S0i3 regression
Keeping the PM timer enabled will disqualify an ADL system from entering
S0i3, and will also cause an increase in power during suspend states.
The PM timer is not required for brya boards, therefore disabling it.
Fixes: 0e905801 (soc/intel: transition full control over PM Timer from
FSP to coreboot)
BUG=b:206922066
TEST=Boot gimble to OS and verify S0i3 counter incrementing after
exiting S0ix suspend states.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I8005dacd732c033980ccc479375ff5b06df8dac1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59790
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
0 files changed, 0 insertions, 0 deletions