diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-09-14 18:11:40 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-21 08:04:00 +0000 |
commit | b8ebeba4a2e42ee04d75712a39b166cb821eeba8 (patch) | |
tree | b8c3d6461ab2d2ca7d180acdb49eb99865b4440f /src/northbridge/intel/sandybridge/registers/epbar.h | |
parent | 3447db5fe451c84c3c8dbb3e4a88c266e6c1d368 (diff) |
nb/intel/sandybridge: Put DMIBAR/EPBAR registers into separate files
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.
Change-Id: I836df4675f4886635973c0c75f5981c9ef17d84b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45359
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/registers/epbar.h')
-rw-r--r-- | src/northbridge/intel/sandybridge/registers/epbar.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/registers/epbar.h b/src/northbridge/intel/sandybridge/registers/epbar.h new file mode 100644 index 0000000000..386dbe1262 --- /dev/null +++ b/src/northbridge/intel/sandybridge/registers/epbar.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SANDYBRIDGE_REGISTERS_EPBAR_H__ +#define __SANDYBRIDGE_REGISTERS_EPBAR_H__ + +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCAP2 0x008 /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#endif /* __SANDYBRIDGE_REGISTERS_EPBAR_H__ */ |