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authorDan Elkouby <streetwalkermc@gmail.com>2018-04-13 18:47:10 +0300
committerPatrick Georgi <pgeorgi@google.com>2018-04-16 08:46:30 +0000
commitdabebc3716bac1dbe9445dfb2bbbbb833ee21de1 (patch)
tree5cc39ad5a948381b6f76a664332bde6077112ebc /src/northbridge/intel/sandybridge/raminit_ivy.c
parent0c024208cdd3cfdfd7689b6fcba1b5c877f550c7 (diff)
nb/intel/sandybridge: support more XMP timings
Tested with a pair of GSkill F3-1866C9-8GSR. This makes sure in particular that we honor the CMD rate requested by the XMP profile. This memory kit needs a CMD rate of 2 to be stable at DDR3-1600 and up, even though it passes training at 1. Also respect requested CWL to match vendor firmware and for a potential increase in performance. The tested kit requests a tighter value than the per-frequency table provides and has shown to be stable using that setting. Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9 Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com> Reviewed-on: https://review.coreboot.org/25664 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_ivy.c')
-rw-r--r--src/northbridge/intel/sandybridge/raminit_ivy.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c
index 675ac7181c..19dea2f2e1 100644
--- a/src/northbridge/intel/sandybridge/raminit_ivy.c
+++ b/src/northbridge/intel/sandybridge/raminit_ivy.c
@@ -479,7 +479,10 @@ static void dram_timing(ramctr_timing *ctrl)
/* DLL_CONFIG_MDLL_W_TIMER */
ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3;
- ctrl->CWL = get_CWL(ctrl->tCK);
+ if (ctrl->tCWL)
+ ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK);
+ else
+ ctrl->CWL = get_CWL(ctrl->tCK);
printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL);
/* Find tRCD */