From dabebc3716bac1dbe9445dfb2bbbbb833ee21de1 Mon Sep 17 00:00:00 2001 From: Dan Elkouby Date: Fri, 13 Apr 2018 18:47:10 +0300 Subject: nb/intel/sandybridge: support more XMP timings Tested with a pair of GSkill F3-1866C9-8GSR. This makes sure in particular that we honor the CMD rate requested by the XMP profile. This memory kit needs a CMD rate of 2 to be stable at DDR3-1600 and up, even though it passes training at 1. Also respect requested CWL to match vendor firmware and for a potential increase in performance. The tested kit requests a tighter value than the per-frequency table provides and has shown to be stable using that setting. Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9 Signed-off-by: Dan Elkouby Reviewed-on: https://review.coreboot.org/25664 Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit_ivy.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/northbridge/intel/sandybridge/raminit_ivy.c') diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 675ac7181c..19dea2f2e1 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -479,7 +479,10 @@ static void dram_timing(ramctr_timing *ctrl) /* DLL_CONFIG_MDLL_W_TIMER */ ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3; - ctrl->CWL = get_CWL(ctrl->tCK); + if (ctrl->tCWL) + ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); + else + ctrl->CWL = get_CWL(ctrl->tCK); printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); /* Find tRCD */ -- cgit v1.2.3