nb/intel/sandybridge: Use bitfields for I/O data timings

Refactor in preparation to split up `program_timings`.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: I68410165f397d8b4f662e40e88fb6a58ab1c5cff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47772
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 28 insertions, 0 deletions

diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index debfaa2f2a..8c92c17ce8 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -98,6 +98,34 @@ struct iosav_ssq {
 	} addr_update;
 };
 
+union gdcr_rx_reg {
+	struct {
+		u32 rcven_pi_code     : 6; /* [ 5.. 0] */
+		u32                   : 2;
+		u32 rx_dqs_p_pi_code  : 7; /* [14.. 8] */
+		u32                   : 1;
+		u32 rcven_logic_delay : 3; /* [18..16] */
+		u32                   : 1;
+		u32 rx_dqs_n_pi_code  : 7; /* [26..20] */
+		u32                   : 5;
+	};
+	u32 raw;
+};
+
+union gdcr_tx_reg {
+	struct {
+		u32 tx_dq_pi_code      :  6; /* [ 5.. 0] */
+		u32                    :  2;
+		u32 tx_dqs_pi_code     :  6; /* [13.. 8] */
+		u32                    :  1;
+		u32 tx_dqs_logic_delay :  3; /* [17..15] */
+		u32                    :  1;
+		u32 tx_dq_logic_delay  :  1; /* [19..19] */
+		u32                    : 12;
+	};
+	u32 raw;
+};
+
 union gdcr_cmd_pi_coding_reg {
 	struct {
 		u32 cmd_pi_code         : 6; /* [ 5.. 0] */