diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-14 16:49:29 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-11-22 20:34:04 +0000 |
| commit | 9426721807e0f531ea198ff932b8548d48550780 (patch) | |
| tree | 9f05125da279c2d1886ba0df8417fcc54366063e /src/northbridge/intel/sandybridge/raminit_common.h | |
| parent | 068c2595f2a3cc57d73849926f420bd6f63d72f6 (diff) | |
nb/intel/sandybridge: Make helper for write leveling sequence
Encapsulate the IOSAV sequence into a helper to help reduce clutter.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I58595a5c53fcdc3f29fa55b015a82cbfe85cd6cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.h')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 10dd59d844..c1fb10b207 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -253,6 +253,8 @@ void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap); void iosav_write_read_mpr_sequence( int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2); +void iosav_write_jedec_write_leveling_sequence( + ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg); void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2); void iosav_write_command_training_sequence( |