From 9426721807e0f531ea198ff932b8548d48550780 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 14 Nov 2020 16:49:29 +0100 Subject: nb/intel/sandybridge: Make helper for write leveling sequence Encapsulate the IOSAV sequence into a helper to help reduce clutter. Tested on Asus P8H61-M PRO, still boots. Change-Id: I58595a5c53fcdc3f29fa55b015a82cbfe85cd6cb Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47615 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/sandybridge/raminit_common.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/northbridge/intel/sandybridge/raminit_common.h') diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 10dd59d844..c1fb10b207 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -253,6 +253,8 @@ void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap); void iosav_write_read_mpr_sequence( int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2); +void iosav_write_jedec_write_leveling_sequence( + ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg); void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2); void iosav_write_command_training_sequence( -- cgit v1.2.3