diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-23 22:19:29 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-25 16:12:20 +0000 |
| commit | 48409b82299ed032e151a67b80b2bb257b463172 (patch) | |
| tree | 95a217644214cddb1ffd9a7f56bed6f94e9fddd8 /src/northbridge/intel/sandybridge/raminit_common.h | |
| parent | df09bdb726e719d2729a55734097e38bdcd7d67b (diff) | |
nb/intel/sandybridge: Cache FRQ index
It does not change once a frequency has been set, so store it somewhere.
Since this changes the saved data definition, update MRC_CACHE_VERSION.
As SNB will eventually use the same code, only IVB is being refactored.
Change-Id: I25b7c394abab173241fffdf57ac5c929daad8257
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.h')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 43bdd340dd..d966c51dfc 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -33,7 +33,7 @@ /* * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! */ -#define MRC_CACHE_VERSION 2 +#define MRC_CACHE_VERSION 3 typedef struct odtmap_st { u16 rttwr; @@ -78,6 +78,9 @@ typedef struct ramctr_timing_st { /* DDR base_freq = 100 Mhz / 133 Mhz */ u8 base_freq; + /* Frequency index */ + u32 FRQ; + u16 cas_supported; /* Latencies are in units of ns, scaled by x256 */ u32 tCK; |