From 48409b82299ed032e151a67b80b2bb257b463172 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Mar 2020 22:19:29 +0100 Subject: nb/intel/sandybridge: Cache FRQ index It does not change once a frequency has been set, so store it somewhere. Since this changes the saved data definition, update MRC_CACHE_VERSION. As SNB will eventually use the same code, only IVB is being refactored. Change-Id: I25b7c394abab173241fffdf57ac5c929daad8257 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39786 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/sandybridge/raminit_common.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/northbridge/intel/sandybridge/raminit_common.h') diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 43bdd340dd..d966c51dfc 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -33,7 +33,7 @@ /* * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! */ -#define MRC_CACHE_VERSION 2 +#define MRC_CACHE_VERSION 3 typedef struct odtmap_st { u16 rttwr; @@ -78,6 +78,9 @@ typedef struct ramctr_timing_st { /* DDR base_freq = 100 Mhz / 133 Mhz */ u8 base_freq; + /* Frequency index */ + u32 FRQ; + u16 cas_supported; /* Latencies are in units of ns, scaled by x256 */ u32 tCK; -- cgit v1.2.3