diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-11-19 12:53:36 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:13:28 +0000 |
commit | 9fbb1b096ff64e83a822d165fb732f22a2ec6e79 (patch) | |
tree | 114937a1f3b5d9a1be3790a43483b329e2fd9ae5 /src/northbridge/intel/sandybridge/raminit_common.c | |
parent | 09fc4b90ebfdb81914f6b89b676db101a417414a (diff) |
nb/intel/sandybridge: Only use write Vref if supported
Only some Ivy Bridge SKUs support write Vref control.
Change-Id: I4e606c69c6758d909946da43c3d243e3af8833cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.c')
-rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d533ca8a30..01dfcc4a7e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2459,6 +2459,13 @@ int discover_timC_write(ramctr_timing *ctrl) int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int channel, slotrank, lane; + /* Changing the write Vref is only supported on some Ivy Bridge SKUs */ + if (!IS_IVY_CPU(ctrl->cpu)) + return 0; + + if (!(pci_read_config32(HOST_BRIDGE, CAPID0_A) & CAPID_WRTVREF)) + return 0; + FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { lower[channel][slotrank][lane] = 0; upper[channel][slotrank][lane] = MAX_TIMC; |