diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-12-07 12:34:36 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-23 16:11:35 +0000 |
| commit | 9f4ed3b5504e564c44f14dce0bab0f9bc92779b6 (patch) | |
| tree | 14425d8a41aeb93b6d4e12c9f312ff96c79dd8e1 /src/northbridge/intel/sandybridge/raminit_common.c | |
| parent | a853e7acdba6b58e2efb57e186ae0d14ea85fad2 (diff) | |
nb/intel/sandybridge: Always wait for IOSAV after starting it
Ensure that IOSAV is finished before continuing. This might solve some
random failures on the I/O and roundtrip latency training algorithm.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: Ic08a40346b6c60e372bada10f9c4ee42eb974f9f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48403
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 9308ed521b..ccf240372c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -680,7 +680,7 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); - iosav_run_once(channel); + iosav_run_once_and_wait(channel); } /* Obtain optimal power down mode for current configuration */ @@ -1332,7 +1332,7 @@ int receive_enable_calibration(ramctr_timing *ctrl) iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 0); - iosav_run_once(channel); + iosav_run_once_and_wait(channel); const union gdcr_training_mod_reg training_mod = { .receive_enable_mode = 1, @@ -1460,7 +1460,7 @@ static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank) iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 18); - iosav_run_once(channel); + iosav_run_once_and_wait(channel); for (tx_dq = 0; tx_dq <= MAX_TX_DQ; tx_dq++) { FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].tx_dq = tx_dq; |