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| author | Elyes Haouas <ehaouas@noos.fr> | 2024-03-23 15:10:04 +0100 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-04-11 19:19:08 +0000 |
| commit | 31402178c56108e752b95c34562b6e3554a2c1d8 (patch) | |
| tree | 0ac4a3cea23ce5c66cc91f2883d3b30184d0f565 /src/northbridge/intel/sandybridge/raminit_common.c | |
| parent | 1dc8f0272bd222125d2d26cfa2b311f3d134f6ca (diff) | |
tree: Remove blank lines before '}' and after '{'
Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3f5e290c57..f896541288 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -64,7 +64,6 @@ void dram_find_common_params(ramctr_timing *ctrl) valid_dimms = 0; FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { - const struct dimm_attr_ddr3_st *dimm = &dimms->dimm[channel][slot]; if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) continue; @@ -1138,7 +1137,6 @@ static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int slotrank, i int lane, i; for (rcven_delta = -25; rcven_delta <= 25; rcven_delta++) { - FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].rcven = upperA[lane] + rcven_delta + QCLK_PI; @@ -1358,7 +1356,6 @@ int receive_enable_calibration(ramctr_timing *ctrl) FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].rcven -= QCLK_PI; upperA[lane] -= QCLK_PI; - } } else if (some_high) { ctrl->timings[channel][slotrank].roundtrip_latency++; @@ -1657,7 +1654,6 @@ static void train_write_flyby(ramctr_timing *ctrl) fill_pattern1(ctrl, channel); } FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { - /* Reset read and write WDB pointers */ mchbar_write32(IOSAV_DATA_CTL_ch(channel), 0x10001); @@ -2501,7 +2497,6 @@ int aggressive_write_training(ramctr_timing *ctrl) upper[channel][slotrank][lane] = MIN(rn.end - ctrl->tx_dq_offset[i], upper[channel][slotrank][lane]); - } } } @@ -2621,7 +2616,6 @@ void channel_scrub(ramctr_timing *ctrl) rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits; for (bank = 0; bank < 8; bank++) { for (row = 0; row < rowsize; row += 16) { - u8 gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD); const struct iosav_ssq sequence[] = { /* |