diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-21 13:12:37 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-23 19:26:35 +0000 |
| commit | 80037f715c9de5a8bb926a0820508d7530e6f429 (patch) | |
| tree | aa0e4e62e0db09515f0cb672b97a5c3e81715f3e /src/northbridge/intel/sandybridge/raminit.c | |
| parent | 5c1baf5bece75de2e396e3f37cfffba310cdf4cd (diff) | |
nb/intel/sandybridge: Store CPUID in ctrl struct
Instead of storing an int with a single bit of information taken from
the CPUID, we might as well store the actual CPUID. And since we are
changing the definition of the saved data, bump the version number.
Tested on Asus P8Z77-V LX2, still boots fine.
Change-Id: I6ac435fb83900a52890f823e7614055061299e23
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39720
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index dc999138f7..2a3e4d73e3 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -227,20 +227,19 @@ static void save_timings(ramctr_timing *ctrl) static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size) { - if (ctrl->sandybridge) + if (IS_SANDY_CPU(ctrl->cpu)) return try_init_dram_ddr3_snb(ctrl, fast_boot, s3resume, me_uma_size); else return try_init_dram_ddr3_ivb(ctrl, fast_boot, s3resume, me_uma_size); } -static void init_dram_ddr3(int min_tck, int s3resume) +static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) { int me_uma_size, cbmem_was_inited, fast_boot, err; ramctr_timing ctrl; spd_raw_data spds[4]; struct region_device rdev; ramctr_timing *ctrl_cached; - u32 cpu; MCHBAR32(SAPMCTL) |= 1; @@ -313,8 +312,7 @@ static void init_dram_ddr3(int min_tck, int s3resume) ctrl.tCK = min_tck; /* Get architecture */ - cpu = cpu_get_cpuid(); - ctrl.sandybridge = IS_SANDY_CPU(cpu); + ctrl.cpu = cpuid; /* Get DDR3 SPD data */ memset(spds, 0, sizeof(spds)); @@ -334,8 +332,7 @@ static void init_dram_ddr3(int min_tck, int s3resume) ctrl.tCK = min_tck; /* Get architecture */ - cpu = cpu_get_cpuid(); - ctrl.sandybridge = IS_SANDY_CPU(cpu); + ctrl.cpu = cpuid; /* Reset DDR3 frequency */ dram_find_spds_ddr3(spds, &ctrl); @@ -385,5 +382,5 @@ void perform_raminit(int s3resume) timestamp_add_now(TS_BEFORE_INITRAM); - init_dram_ddr3(get_mem_min_tck(), s3resume); + init_dram_ddr3(get_mem_min_tck(), s3resume, cpu_get_cpuid()); } |