diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-05-02 20:00:32 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-05-21 18:27:13 +0000 |
| commit | b631d07494805d7e3c7729ebd12c25f2166ff550 (patch) | |
| tree | 301a3ac39cf3d80c20728b9e82f2bfef43b3d2c2 /src/northbridge/intel/sandybridge/mchbar_regs.h | |
| parent | 7ed04e460d4e3e99af82c4bb445e4e1b3ac1dd47 (diff) | |
nb/intel/sandybridge: Refactor IOSAV_SUBSEQUENCE again
To replace the register writes with assignments to struct fields, we
would need to have the values as parameters of a single macro. So,
split the raw value of `IOSAV_n_SP_CMD_CTRL_ch` in two parts. Note that
the single command that sets bit 17 is likely wrong, but it will be
fixed after refactoring. For now, we'll treat it as part of `ranksel`.
Move the parameters of `ADDR_UPDATE` into the top-level IOSAV macro.
Hopefully, this will be enough to replace the underlying implementation.
Line length limits are not for review. Breaking the lines unnecessarily
complicates search and replace operations, and wil be taken care of in
subsequent commits.
Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged.
Change-Id: I404edbd5d90ddc2a6993f39f552480d1ef24e153
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/sandybridge/mchbar_regs.h')
| -rw-r--r-- | src/northbridge/intel/sandybridge/mchbar_regs.h | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h index ba0f7d5952..446861b4b7 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -213,18 +213,12 @@ ((rate) << 12) | \ ((xors) << 16)) -/* Marker macro for IOSAV_n_ADDR_UPDATE */ -#define ADDR_UPDATE_NONE 0 - -/* Only programming the wraparound without any triggers is suspicious */ -#define ADDR_UPDATE_WRAP(wrap) ((wrap) << 5) - -#define IOSAV_SUBSEQUENCE(ch, n, sp_cmd_ctrl, reps, gap, post, dir, addr, rowbits, bank, rank, addr_update) \ +#define IOSAV_SUBSEQUENCE(ch, n, cmd, ranksel, reps, gap, post, dir, addr, rowbits, bank, rank, addr_1, addr_8, upd_bank, upd_rank, wrap, lfsr, rate, xors) \ do { \ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, n)) = sp_cmd_ctrl; \ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, n)) = (cmd) | ((ranksel) << 16); \ MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, n)) = SUBSEQ_CTRL(reps, gap, post, dir); \ MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, n)) = SP_CMD_ADDR(addr, rowbits, bank, rank); \ - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, n)) = addr_update; \ + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, n)) = ADDR_UPDATE(addr_1, addr_8, upd_bank, upd_rank, wrap, lfsr, rate, xors); \ } while (0) /* Indexed register helper macros */ |