diff options
author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2020-07-27 16:23:36 +0200 |
---|---|---|
committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-30 22:45:54 +0000 |
commit | 42609d807ba598fc09035717c32f04aa9b0e73c3 (patch) | |
tree | 3b032b791612fb7e5a82fd64197f7695cfcfd4fc /src/northbridge/intel/sandybridge/hostbridge_regs.h | |
parent | 5e007808cd380fe934b1a3f0c42eb79cb03787d0 (diff) |
nb/intel/*: Fill in SMBIOS type 16 on SNB/HSW
Fill in the maximum DRAM capacity and slot count read from CAPID0_A
registers on Sandy Bridge and Haswell.
While the register isn't part of the Core Series datasheet, it can be
found in the corresponding "Intel Open Source Graphics Programmer's
Reference" datasheets.
Note that the values for DDRSZ (maximum allowed memory size per channel)
need to be halved when only one DIMM per channel is supported. On mobile
platforms, all but quad-core processors are subject to this restriction.
Tested on Lenovo X230:
On Linux, verify that `dmidecode -t 16` reports the actual maximum
capacity (16 GiB) instead of the currently-installed capacity (4 GiB) or
the max capacity assuming two DIMMs per channel is possible (32 GiB).
Change-Id: I6e2346de1ffe52e8685276acbdbf25755f4cc162
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/hostbridge_regs.h')
-rw-r--r-- | src/northbridge/intel/sandybridge/hostbridge_regs.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/hostbridge_regs.h b/src/northbridge/intel/sandybridge/hostbridge_regs.h index 00d37d4a6d..2d2fcff3b1 100644 --- a/src/northbridge/intel/sandybridge/hostbridge_regs.h +++ b/src/northbridge/intel/sandybridge/hostbridge_regs.h @@ -49,6 +49,11 @@ #define TOLUD 0xbc /* Top of Low Used Memory */ #define CAPID0_A 0xe4 /* Capabilities Register A */ +#define CAPID_ECCDIS (1 << 25) +#define CAPID_DDPCD (1 << 14) +#define CAPID_PDCD (1 << 12) +#define CAPID_DDRSZ(x) (((x) >> 19) & 0x3) + #define CAPID0_B 0xe8 /* Capabilities Register B */ #define SKPAD 0xdc /* Scratchpad Data */ |