diff options
| author | Franklin Lin <franklin_lin@wistron.corp-partner.google.com> | 2022-07-15 17:53:13 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-20 12:36:52 +0000 |
| commit | 759bb4c00d818011c754e62afbe554b6a4cb52d4 (patch) | |
| tree | 4f43bf68575536994a353e40854f1cdd0eca2b8d /src/northbridge/intel/sandybridge/gma.c | |
| parent | e69851cd8a2efd9ccffe14465fe7fdbb5c93eed1 (diff) | |
soc/intel/alderlake/fsp_params.c: Set DdrSpeedControl UPD
When override "max_dram_speed_mts", set the DdrSpeedControl to manual.
(0:Auto, 1:Manual)
BUG=b:229549930
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com>
Change-Id: Iffbbee8082fb1a41e0ed1db3f4ea9ec4709c9ce7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65877
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/gma.c')
0 files changed, 0 insertions, 0 deletions