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authorMichał Żygowski <michal.zygowski@3mdeb.com>2020-03-20 16:19:55 +0100
committerMichał Żygowski <michal.zygowski@3mdeb.com>2020-03-25 08:05:43 +0000
commit8e46d42009f8d8f24787fcaa9785d62ae9260786 (patch)
tree50fc8758fa3bdfc31c0d18bf219dfcc2ce6eac88 /src/northbridge/intel/sandybridge/common.c
parentc04871a398ca945b42fde0867572094c38f6f92c (diff)
mb/pcengines/apu2: enable PCIe power management features
Enable ASPM L0s and L1, Common Clock and Clock Power Management for all PCIe ports. TEST=boot Debian linux and check new PCIe capabilities appear in lspci Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I0a4c83731742f31ab8ef1d326e800dfdc2abb1b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge/intel/sandybridge/common.c')
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