diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 08:47:33 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-30 15:58:19 +0000 |
| commit | fade723b2551d12c98c91c968d213eeb827d856d (patch) | |
| tree | f504f6adce43761ac9cb76498279fea0686074be /src/northbridge/intel/sandybridge/chipset.cb | |
| parent | 691d58f9996d2ff3820b2c08646e98f16bbde2ee (diff) | |
nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree
Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69291
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/chipset.cb')
| -rw-r--r-- | src/northbridge/intel/sandybridge/chipset.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index ae02a5b927..e7ade1977e 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -2,6 +2,7 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on + ops sandybridge_cpu_bus_ops chip cpu/intel/model_206ax # Magic APIC ID to locate this chip device lapic 0 on end @@ -14,5 +15,6 @@ chip northbridge/intel/sandybridge end device domain 0 on + ops sandybridge_pci_domain_ops end end |