diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 14:58:32 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-30 23:11:36 +0000 |
| commit | 10f9b83f534bdc89e00f0a02befd952ae8d7f829 (patch) | |
| tree | 01b2bf7eaa935ec979921a956528c9fafb9faa28 /src/northbridge/intel/sandybridge/bootblock.c | |
| parent | 32770f840d768b46d123893ecb87bb9095e4655d (diff) | |
nb/intel/sandybridge: Define and use MMCONF_BUS_NUMBER
Change-Id: Id88c18129bb773d979ad84bd0bb47188d74d4bc4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49762
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/bootblock.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/bootblock.c | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index bea85f4f8e..529f4f886d 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -1,13 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> +#include <assert.h> #include <device/pci_ops.h> +#include <types.h> #include "sandybridge.h" -void bootblock_early_northbridge_init(void) +static uint32_t encode_pciexbar_length(void) { - uint32_t reg; + switch (CONFIG_MMCONF_BUS_NUMBER) { + case 256: return 0 << 1; + case 128: return 1 << 1; + case 64: return 2 << 1; + default: return dead_code_t(uint32_t); + } +} +void bootblock_early_northbridge_init(void) +{ /* * The "io" variant of the config access is explicitly used to setup the * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all @@ -18,8 +28,7 @@ void bootblock_early_northbridge_init(void) * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - reg = 0; - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); } |