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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 16:15:09 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-24 13:43:58 +0000 |
| commit | 20f71369d95d9691e668455b2262c80997fc8c3f (patch) | |
| tree | cd1bc72b2e5578f3e6b1f9dbde2441a4f3459ceb /src/northbridge/intel/sandybridge/acpi.c | |
| parent | c3e9ba03b6e8f888680b0117df8d6405eebfd01a (diff) | |
nb/intel/pineview: Put stage cache in TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Tested on Foxconn D41S.
Change-Id: I3d163e8ff328ba01425b524a673f34a96fb93ea7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25605
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/acpi.c')
0 files changed, 0 insertions, 0 deletions