northbridge/intel/pineview: Add remaining boilerplate code for northbridge

This patch does *not* include native raminit

Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12430
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)

1 files changed, 131 insertions, 2 deletions

diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
index 4b3b0b189c..d8073402a5 100644
--- a/src/northbridge/intel/pineview/pineview.h
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -20,6 +20,16 @@
 #include <northbridge/intel/pineview/iomap.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 
+#define BOOT_PATH_NORMAL	0
+#define BOOT_PATH_RESET		1
+#define BOOT_PATH_RESUME	2
+
+#define SYSINFO_DIMM_NOT_POPULATED	0x00
+#define SYSINFO_DIMM_X16SS		0x01
+#define SYSINFO_DIMM_X16DS		0x02
+#define SYSINFO_DIMM_X8DS		0x05
+#define SYSINFO_DIMM_X8DDS		0x06
+
 /* Device 0:0.0 PCI configuration space (Host Bridge) */
 
 #define EPBAR		0x40
@@ -58,7 +68,7 @@
 #define TOUUD		0xa2
 #define GBSM		0xa4
 #define BGSM		0xa8
-#define TSEGMB		0xac
+#define TSEG		0xac
 #define TOLUD		0xb0	/* Top of Low Used Memory */
 #define ERRSTS		0xc8
 #define ERRCMD		0xca
@@ -77,7 +87,6 @@
 #define BCTRL1		0x3e	/* 16bit */
 #define PEGSTS		0x214	/* 32bit */
 
-
 /* Device 0:2.0 PCI configuration space (Graphics Device) */
 
 #define GMADR		0x18
@@ -85,6 +94,7 @@
 #define BSM		0x5c
 #define GCFC		0xf0	/* Graphics Clock Frequency & Gating Control */
 
+#define GPIO32(x) *((volatile u32 *)(DEFAULT_GPIOBASE + x))
 
 /*
  * MCHBAR
@@ -110,7 +120,126 @@
 #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
 #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
 
+enum fsb_clk {
+	FSB_CLOCK_667MHz = 0,
+	FSB_CLOCK_800MHz = 1,
+};
+
+enum mem_clk {
+	MEM_CLOCK_667MHz = 0,
+	MEM_CLOCK_800MHz = 1,
+};
+
+enum ddr {
+	DDR2 = 2,
+	DDR3 = 3,
+};
+
+enum chip_width { /* as in DDR3 spd */
+	CHIP_WIDTH_x4	= 0,
+	CHIP_WIDTH_x8	= 1,
+	CHIP_WIDTH_x16	= 2,
+	CHIP_WIDTH_x32	= 3,
+};
+
+enum chip_cap { /* as in DDR3 spd */
+	CHIP_CAP_256M	= 0,
+	CHIP_CAP_512M	= 1,
+	CHIP_CAP_1G	= 2,
+	CHIP_CAP_2G	= 3,
+	CHIP_CAP_4G	= 4,
+	CHIP_CAP_8G	= 5,
+	CHIP_CAP_16G	= 6,
+};
+
+struct timings {
+	unsigned int	CAS;
+	enum fsb_clk	fsb_clock;
+	enum mem_clk	mem_clock;
+	unsigned int	tRAS;
+	unsigned int	tRP;
+	unsigned int	tRCD;
+	unsigned int	tWR;
+	unsigned int	tRFC;
+	unsigned int	tWTR;
+	unsigned int	tRRD;
+	unsigned int	tRTP;
+};
+
+struct dimminfo {
+	unsigned int	card_type; /* 0x0: unpopulated,
+				      0xa - 0xf: raw card type A - F */
+	u8		type;
+	enum chip_width	width;
+	enum chip_cap	chip_capacity;
+	unsigned int	page_size; /* of whole DIMM in Bytes (4096 or 8192) */
+	unsigned int	sides;
+	unsigned int	banks;
+	unsigned int	ranks;
+	unsigned int	rows;
+	unsigned int	cols;
+	unsigned int	cas_latencies;
+	unsigned int	tAAmin;
+	unsigned int	tCKmin;
+	unsigned int	tWR;
+	unsigned int	tRP;
+	unsigned int	tRCD;
+	unsigned int	tRAS;
+	unsigned int	rank_capacity_mb; /* per rank in Mega Bytes */
+	u8		spd_data[256];
+};
+
+struct pllparam {
+	u8 kcoarse[2][72];
+	u8 pi[2][72];
+	u8 dben[2][72];
+	u8 dbsel[2][72];
+	u8 clkdelay[2][72];
+};
+
+struct sysinfo {
+	u8 maxpi;
+	u8 pioffset;
+	u8 pi[8];
+	u16 coarsectrl;
+	u16 coarsedelay;
+	u16 mediumphase;
+	u16 readptrdelay;
+
+	int		txt_enabled;
+	int		cores;
+	int		boot_path;
+	int		max_ddr2_mhz;
+	int		max_ddr3_mt;
+	int		max_fsb_mhz;
+	int		max_render_mhz;
+	int		enable_igd;
+	int		enable_peg;
+	u16		ggc;
+
+	int		dimm_config[2];
+	int		dimms_per_ch;
+	int		spd_type;
+	int		channel_capacity[2];
+	struct timings	selected_timings;
+	struct dimminfo	dimms[4];
+	u8		spd_map[4];
+
+	u8 nodll;
+	u8 async;
+	u8 dt0mode;
+	u8 mvco4x;		/* 0 (8x) or 1 (4x) */
+};
+
+void pineview_early_initialization(void);
+u32 decode_igd_memory_size(const u32 gms);
+u32 decode_igd_gtt_size(const u32 gsm);
+u8 decode_pciebar(u32 *const base, u32 *const len);
+
 /* provided by mainboard code */
 void setup_ich7_gpios(void);
 
+struct acpi_rsdp;
+unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp);
+
 #endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */