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authorAngel Pons <th3fanbus@gmail.com>2020-08-03 15:40:54 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-04 21:27:16 +0000
commit653d8717ba8d785af4e4eafca2416e1da2988f5d (patch)
tree366317d6807b347467e964a2979d35859b71a959 /src/northbridge/intel/pineview/pineview.h
parent69356489fe43ca36f5ed20b7b92dc2cd0641803d (diff)
nb/intel/pineview: Change signature of `decode_pciebar`
Rename it and make it return an int, like other northbridges do. Change-Id: Id526ff893320a77e96767ec642c196c2196f84e1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/pineview/pineview.h')
-rw-r--r--src/northbridge/intel/pineview/pineview.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
index d557d22f2d..47257ddb48 100644
--- a/src/northbridge/intel/pineview/pineview.h
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -185,7 +185,7 @@ struct sysinfo {
void pineview_early_init(void);
u32 decode_igd_memory_size(const u32 gms);
u32 decode_igd_gtt_size(const u32 gsm);
-u8 decode_pciebar(u32 *const base, u32 *const len);
+int decode_pcie_bar(u32 *const base, u32 *const len);
/* Mainboard romstage callback functions */
void get_mb_spd_addrmap(u8 *spd_addr_map);