nb/intel/pineview: Use common code for SMM in TSEG

This also caches the TSEG region and therefore increases MTRR usage a
little in some cases.

Change-Id: I5f947cfae730b67bc76a581bc90cb10e5a2a4a52
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25598
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 31 insertions, 0 deletions

diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 2647bcc968..192c24edb2 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -27,6 +27,7 @@
 #include <boot/tables.h>
 #include <arch/acpi.h>
 #include <northbridge/intel/pineview/pineview.h>
+#include <cpu/intel/smm/gen1/smi.h>
 
 /* Reserve everything between A segment and 1MB:
  *
@@ -141,6 +142,36 @@ static void mch_domain_read_resources(struct device *dev)
 	add_fixed_resources(dev, index);
 }
 
+void northbridge_write_smram(u8 smram)
+{
+	struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+
+	if (dev == NULL)
+		die("could not find pci 00:00.0!\n");
+
+	pci_write_config8(dev, SMRAM, smram);
+}
+
+/*
+ * Really doesn't belong here but will go away with parallel mp init,
+ * so let it be here for a while...
+ */
+int cpu_get_apic_id_map(int *apic_id_map)
+{
+	unsigned int i;
+
+	/* Logical processors (threads) per core */
+	const struct cpuid_result cpuid1 = cpuid(1);
+	/* Read number of cores. */
+	const char cores = (cpuid1.ebx >> 16) & 0xf;
+
+	/* TODO in parallel MP cpuid(1).ebx */
+	for (i = 0; i < cores; i++)
+		apic_id_map[i] = i;
+
+	return cores;
+}
+
 static void mch_domain_set_resources(struct device *dev)
 {
 	struct resource *res;