From de6bda63d9890ac88a01368314fcf0802a694cf4 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 10 Apr 2018 13:40:39 +0200 Subject: nb/intel/pineview: Use common code for SMM in TSEG This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Change-Id: I5f947cfae730b67bc76a581bc90cb10e5a2a4a52 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/25598 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/pineview/northbridge.c | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'src/northbridge/intel/pineview/northbridge.c') diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 2647bcc968..192c24edb2 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -27,6 +27,7 @@ #include #include #include +#include /* Reserve everything between A segment and 1MB: * @@ -141,6 +142,36 @@ static void mch_domain_read_resources(struct device *dev) add_fixed_resources(dev, index); } +void northbridge_write_smram(u8 smram) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + + if (dev == NULL) + die("could not find pci 00:00.0!\n"); + + pci_write_config8(dev, SMRAM, smram); +} + +/* + * Really doesn't belong here but will go away with parallel mp init, + * so let it be here for a while... + */ +int cpu_get_apic_id_map(int *apic_id_map) +{ + unsigned int i; + + /* Logical processors (threads) per core */ + const struct cpuid_result cpuid1 = cpuid(1); + /* Read number of cores. */ + const char cores = (cpuid1.ebx >> 16) & 0xf; + + /* TODO in parallel MP cpuid(1).ebx */ + for (i = 0; i < cores; i++) + apic_id_map[i] = i; + + return cores; +} + static void mch_domain_set_resources(struct device *dev) { struct resource *res; -- cgit v1.2.3