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authorDamien Zammit <damien@zamaudio.com>2016-01-18 16:37:41 +1100
committerMartin Roth <martinroth@google.com>2016-01-20 16:26:22 +0100
commit02f4764bf362170d4d101bac90b48bb32d106a21 (patch)
treecaa239fd16b3d5babae9ab1282931702f67d0d4c /src/northbridge/intel/pineview/northbridge.c
parentfb456e61a9d8b86f852d84e40ffb340d3ce5d3d7 (diff)
nb/intel/pineview: Use macro names for memory base registers
Change-Id: I0b79ddcf9248c6a6964dd60e30a6ea18e27bc186 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13032 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/intel/pineview/northbridge.c')
-rw-r--r--src/northbridge/intel/pineview/northbridge.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 21f133dfb2..0f534dc163 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -45,15 +45,15 @@ static void mch_domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
/* Top of Upper Usable DRAM, including remap */
- touud = pci_read_config16(dev, 0xa2);
+ touud = pci_read_config16(dev, TOUUD);
touud <<= 20;
/* Top of Lower Usable DRAM */
- tolud = pci_read_config16(dev, 0xb0) & 0xfff0;
+ tolud = pci_read_config16(dev, TOLUD) & 0xfff0;
tolud <<= 16;
/* Top of Memory - does not account for any UMA */
- tom = pci_read_config16(dev, 0xa0) & 0x1ff;
+ tom = pci_read_config16(dev, TOM) & 0x1ff;
tom <<= 27;
printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",