From 02f4764bf362170d4d101bac90b48bb32d106a21 Mon Sep 17 00:00:00 2001 From: Damien Zammit Date: Mon, 18 Jan 2016 16:37:41 +1100 Subject: nb/intel/pineview: Use macro names for memory base registers Change-Id: I0b79ddcf9248c6a6964dd60e30a6ea18e27bc186 Signed-off-by: Damien Zammit Reviewed-on: https://review.coreboot.org/13032 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/northbridge/intel/pineview/northbridge.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/northbridge/intel/pineview/northbridge.c') diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 21f133dfb2..0f534dc163 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -45,15 +45,15 @@ static void mch_domain_read_resources(device_t dev) pci_domain_read_resources(dev); /* Top of Upper Usable DRAM, including remap */ - touud = pci_read_config16(dev, 0xa2); + touud = pci_read_config16(dev, TOUUD); touud <<= 20; /* Top of Lower Usable DRAM */ - tolud = pci_read_config16(dev, 0xb0) & 0xfff0; + tolud = pci_read_config16(dev, TOLUD) & 0xfff0; tolud <<= 16; /* Top of Memory - does not account for any UMA */ - tom = pci_read_config16(dev, 0xa0) & 0x1ff; + tom = pci_read_config16(dev, TOM) & 0x1ff; tom <<= 27; printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", -- cgit v1.2.3