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| author | Sean Rhodes <sean@starlabs.systems> | 2022-07-19 11:20:05 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-20 12:37:21 +0000 |
| commit | e71ea1e1b6a7769ae74f9933f5ae0321d85b2e3d (patch) | |
| tree | 6e036103fedc7f5645b9b48103068541e4c61a32 /src/northbridge/intel/pineview/early_init.c | |
| parent | 759bb4c00d818011c754e62afbe554b6a4cb52d4 (diff) | |
soc/apollolake: Add CSE Firmware Status Registers
Add the CSE, General Status and Miscellaneous registers and
print information from them accordingly. All values were taken
from Intel document number 571993.
Tested on the StarLite Mk III and the correct values are
shown:
[DEBUG] CSE: Working State : 2
[DEBUG] CSE: Manufacturing Mode : NO
[DEBUG] CSE: Operation State : 1
[DEBUG] CSE: FW Init Complete : NO
[DEBUG] CSE: Error Code : 3
[DEBUG] CSE: Operation Mode : 0
[DEBUG] CSE: FPF status : unknown
Please note, the values shown are in an error state.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1a5548132dadbb188a33a7ae30a0a1fa144d130f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/pineview/early_init.c')
0 files changed, 0 insertions, 0 deletions