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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-04-26 22:22:38 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-28 20:14:02 +0000 |
| commit | 932cd22487e248306e43a5742176258eabdfc314 (patch) | |
| tree | 175b5a7ab0b8d8909ea6d29db5d776082267c398 /src/northbridge/intel/pineview/early_init.c | |
| parent | 0de53be394deefe093b79c3b85f453023173fa98 (diff) | |
soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window
This ports back commit d75ee46d3ce6 ("soc/amd/picasso/acpi: Change PCI0
BAR window") to Stoneyridge so that the correct end of the non-fixed
MMIO region gets reported in PCI0's _CRS method.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/northbridge/intel/pineview/early_init.c')
0 files changed, 0 insertions, 0 deletions