diff options
| author | Damien Zammit <damien@zamaudio.com> | 2015-11-14 00:59:21 +1100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-12-02 00:26:36 +0100 |
| commit | f7060f1d0f72bab5b349846bc97784895643cf50 (patch) | |
| tree | 574f7009570b404134446221fda5c82f2717bd14 /src/northbridge/intel/pineview/acpi/pineview.asl | |
| parent | 1a38374535df694a1a63d1f198d9828249019390 (diff) | |
northbridge/intel/pineview: Add remaining boilerplate code for northbridge
This patch does *not* include native raminit
Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12430
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel/pineview/acpi/pineview.asl')
| -rw-r--r-- | src/northbridge/intel/pineview/acpi/pineview.asl | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl new file mode 100644 index 0000000000..d32a906835 --- /dev/null +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "hostbridge.asl" +#include "../iomap.h" +#include <southbridge/intel/i82801gx/i82801gx.h> + +/* PCI Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + + /* This does not seem to work correctly yet - set values statically for + * now. + */ + + Name (PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) /* RCBA */ + Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) + Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000) + Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */ + Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */ + Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */ + }) + + /* Current Resource Settings */ + Method (_CRS, 0, Serialized) + { + Return(PDRS) + } +} + +// PCIe graphics port 0:1.0 +#include "peg.asl" |