diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-07-07 03:00:24 +0200 |
---|---|---|
committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-08 22:09:34 +0000 |
commit | 4d962b2ecf25c82987a3456160c4566da34946d7 (patch) | |
tree | 6e7aa8b23e75585c131cbb51fe80f79eee59cdd8 /src/northbridge/intel/pineview/acpi/hostbridge.asl | |
parent | f67bf49ead50ca07e6483b8b209ee1ab1bfa1e7e (diff) |
nb/intel/pineview: Tidy up comments and cosmetics
Remove some unneeded newlines, add some commas for consistency and
relocate comments to match the code.
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.
Change-Id: I0ac18a692bf613c75083c4aa1860e0a9f07e68d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/pineview/acpi/hostbridge.asl')
-rw-r--r-- | src/northbridge/intel/pineview/acpi/hostbridge.asl | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/src/northbridge/intel/pineview/acpi/hostbridge.asl b/src/northbridge/intel/pineview/acpi/hostbridge.asl index 434ed07176..0a9897c69d 100644 --- a/src/northbridge/intel/pineview/acpi/hostbridge.asl +++ b/src/northbridge/intel/pineview/acpi/hostbridge.asl @@ -24,7 +24,7 @@ Device (MCHC) , 13, MHBR, 22, /* MCHBAR */ - Offset (0x60), /* PCIec BAR */ + Offset (0x60), /* PCIe BAR */ PXEN, 1, /* Enable */ PXSZ, 2, /* BAR size */ , 23, @@ -35,7 +35,7 @@ Device (MCHC) , 11, /* DMBR, 20, /* DMIBAR */ - // ... + /* ... */ Offset (0x90), /* PAM0 */ , 4, @@ -73,18 +73,14 @@ Device (MCHC) , 2, Offset (0xa0), /* Top of Memory */ - TOM, 8, + TOM, 8, Offset (0xb0), /* Top of Low Used Memory */ , 4, TLUD, 12, - } - } - -/* Current Resource Settings */ Name (MCRS, ResourceTemplate() { /* Bus Numbers */ @@ -199,6 +195,7 @@ Name (MCRS, ResourceTemplate() 0x00005000,,, TPMR) }) +/* Current Resource Settings */ Method (_CRS, 0, Serialized) { /* Find PCI resource area in MCRS */ @@ -206,7 +203,8 @@ Method (_CRS, 0, Serialized) CreateDwordField(MCRS, ^PM01._MAX, PMAX) CreateDwordField(MCRS, ^PM01._LEN, PLEN) - /* Fix up PCI memory region: + /* + * Fix up PCI memory region: * Enter actual TOLUD. The TOLUD register contains bits 27-31 of * the top of memory address. */ |