diff options
| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-01-09 11:13:18 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-01-23 19:56:52 +0100 |
| commit | bca985557e3a7dc94c954d7295a963f654886a08 (patch) | |
| tree | d3504e6930d0e8dcd343a60f80f664bdf6239443 /src/northbridge/intel/nehalem/early_init.c | |
| parent | f7a42de725b2e5a2a7e3af7cee61291c56cd6518 (diff) | |
X201: Move early nehalem S3 magic to right place.
This MCH magic needs to be done before GPIO.
Now S3 (Suspend-to-RAM) works on X201.
Change-Id: I319e57af52ff01083bfbffbcd883ac5f453320a1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4632
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/northbridge/intel/nehalem/early_init.c')
| -rw-r--r-- | src/northbridge/intel/nehalem/early_init.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 81bac87c2f..ee8c17a18c 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -166,4 +166,10 @@ void nehalem_early_initialization(int chipset_type) pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, DEFAULT_HECIBAR); pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + + /* Magic for S3 resume. Must be done early. */ + if (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) { + MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6; + MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4; + } } |