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| author | Zhanyong Wang <zhanyong.wang@mediatek.com> | 2020-05-14 13:27:03 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-12 08:55:53 +0000 |
| commit | 06639f2abf86bd0eef9c7808b7e724450d1408b8 (patch) | |
| tree | 26201f0c284e772f312dcb55f0e4ea04490fecea /src/northbridge/intel/ironlake | |
| parent | 5acea15d63e821a1bc416d206162ed030cd5d57c (diff) | |
soc/mediatek/mt8192: Refactor USB code among similar SoCs
Adjust ssusb register layout and offset accroding mt8192 Soc
then refactor USB code which will be reused among similar SoCs
Signed-off-by: Tianping Fang <tianping.fang@mediatek.com>
Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
Change-Id: Icb4cc304654b5fb7cf20b96ab83a22663bfeab63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/northbridge/intel/ironlake')
0 files changed, 0 insertions, 0 deletions