diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 16:29:54 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:30:50 +0000 |
| commit | 3ab19b32a2d417a03e2b3d9942eae981dd951233 (patch) | |
| tree | dc5c5044388a287b9ece26cf9a97a6bac2ef1f8b /src/northbridge/intel/ironlake/bootblock.c | |
| parent | 16fe1e0246df10fd9bac30c091b38d454d96cc89 (diff) | |
nb/intel/ironlake: Add definition for SAD PCI device
Let's hope this cheers up the poor System Address Decoder device.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: Ia62c05abb07216dc1ba449c3a17f8d53050b5af1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/ironlake/bootblock.c')
| -rw-r--r-- | src/northbridge/intel/ironlake/bootblock.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index d40b0b5d54..50e7adbb93 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -2,9 +2,10 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> +#include "ironlake.h" void bootblock_early_northbridge_init(void) { - pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); - pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0); + pci_io_write_config32(QPI_SAD, 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); + pci_io_write_config32(QPI_SAD, 0x54, 0); } |