From 3ab19b32a2d417a03e2b3d9942eae981dd951233 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 22 Jul 2020 16:29:54 +0200 Subject: nb/intel/ironlake: Add definition for SAD PCI device Let's hope this cheers up the poor System Address Decoder device. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: Ia62c05abb07216dc1ba449c3a17f8d53050b5af1 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43732 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/ironlake/bootblock.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/ironlake/bootblock.c') diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index d40b0b5d54..50e7adbb93 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -2,9 +2,10 @@ #include #include +#include "ironlake.h" void bootblock_early_northbridge_init(void) { - pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); - pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0); + pci_io_write_config32(QPI_SAD, 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); + pci_io_write_config32(QPI_SAD, 0x54, 0); } -- cgit v1.2.3